1. Field of the Invention
The present invention relates generally to analog-to-digital converters and, more particularly, to pipelined analog-to-digital converters.
2. Description of the Related Art
Each converter stage of an N-bit pipelined ADC successively realizes at least one respective level in a successive approximation of an analog input signal. Although the conversion of each input analog signal requires N cycles, the pipeline architecture allows N conversions (each at a different respective level) to proceed simultaneously with a digital output signal thereby produced each cycle. Accordingly, pipelined ADC structures realize extremely high throughput rates and facilitate identical stage structures. Without some form of correction, however, the converter stages of pipelined ADCs typically generate signal processing errors which degrade the overall signal conversion.
One exemplary converter stage structure for pipelined ADCs compares its respective analog input to a single reference (e.g., ground) and, in response to this comparison, generates a 1-bit digital signal which is provided to a succeeding converter stage as an digital input signal Din. In addition, this structure provides the succeeding converter stage with an analog residue signal Sres which is an amplified difference between the respective analog input and an analog version of Din.
A widely used structure for generating the analog residue signal Sres comprises an amplifier and an arrangement of switched capacitors. This is an effective and economical converter stage structure which facilitates integrated circuit fabrication but, in practice, it typically introduces errors into the analog residue signal Sres because of signal processing errors which include charge-injection errors (due to switching actions), comparator-offset errors and capacitor-mismatch errors.
Another exemplary pipelined converter stage compares its respective analog input to a pair of spaced references (e.g., xc2x1Vref) to thereby generate a 1.5-bit digital input signal Din (in which Din has three possible values rather than two) and a corresponding analog residue signal Sres which are both passed to a succeeding converter stage. This signal redundancy effectively reduces errors due to comparator offset but has no effect on capacitor-mismatch errors.
Although calibration procedures have been proposed to correct the capacitor-mismatch errors (e.g., see U.S. Pat. Nos. 5,499,027, 5,510,789, 5,668,549, 6,184,809 and 6,232,898), they generally suffer from a variety of disadvantages, e.g., they are difficult to implement, time consuming and require additional converter structure and/or additional conversion process steps,
The present invention is directed to self-calibration methods and structures for pipelined ADCs which can be realized without requiring external measuring instruments or calibrators, without requiring major changes in pipeline structure and which can be rapidly obtained with stored calibration processes.
In particular method embodiments of the invention, each of selected converter stages are calibrated by using succeeding stages as sub-ADCs which measure gain error at a transition step in a selected stage""s residue transfer characteristic and saves the gain error as a calibration constant Ccal for that stage.
After a first calibration constant Ccal has been obtained, the process is successively repeated for preceding converter stages except hat previously-obtained calibration constants are multiplied by their respective stage""s digital input signals Din to obtain weighted calibration constants Ccalwtd which are included in measured gain errors to thereby obtain preceding calibration constants Ccal.
If desired, the ADC calibration processes of the invention can be disabled and the same ADC operated without calibration.
The invention also teaches methods for economically storing the calibration constants Ccal as incremental constants Cinc from which the calibration constants can be recovered when needed.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.